Podcast #128: We chat with Kent C Dodds about why he loves React and discuss what life was like in the dark days before Git. Listen now.


About Me: Verilog and Vimthusiast.

Working in the electronics industry, Audio ASICs specifically.

Welcome constructive feedback via comments to my answers and questions, Edits to correct grammar, spelling, adding context or expanding answers are also welcomed/wanted.

I occasionally add Answer & Question combos for basic questions which come up time and again but never in a generic format with useful titles.

Some Quick Verilog Guides written in the Q&A style

  1. How to implement a (pseudo) hardware random number generator.
  2. Verilog: How to instantiate a module.

The SystemVerilog IEEE 1800-2012 Standard

Next section is shamelessly copied from johnsyweb, he left no contact details so I can not even let him know :(

On Down-voting : About two percent of my votes are down-votes, which I think is quite low. Down-voting is an important part of StackExchange and helps separate the good answers (and questions) from the not-so-good. If I have down-voted one of your posts, I will try to leave a comment as to why. If you down-vote one of my posts, I ask that you, too, leave a comment as to why so that I can either improve my post or remove it. Thank you.

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